Title: Sr. ASIC DSP Design Engineer.
Location: Irvine, CA or San Diego, CA
Type: Full-time Employee
Digital Signal processing is key. Communication type design experience is a must have. Satellite, wireless etc understands communication theory and algorithms for ASIC RTL design. Fixed point implementation for blocks like Reedsolomon, FFT, LDPC, FIR IIR filters
Responsibilities
• Micro-architecture definition for communication/DSP functions including algorithm optimization feedback to Communication Systems team to minimize power and area
• RTL implementation in SystemVerilog/Verilog of communication/DSP functions
• Block-level verification including creation of Verilog or UVM testbenches
• System-level verification in UVM/SysC environment including test case creation/debug, functional coverage specification, and code coverage analysis
• Perform block-level preliminary synthesis and power estimation, including SDC constraint specification and vector-driven power analysis
• Perform block-level design checks including lint, CDC and DFT-readiness checks
• Support Emulator/FPGA-based verification including debug of SW driven test cases
• Post silicon bring-up support and silicon debug in lab
Qualifications
• Solid background in high-speed, low-power implementation of communication/DSP functions, including knowledge of communication/DSP theory and experience with fixed-point implementation
• Strong logical and creative problem-solving skills with excellent analytical and debugging skills
• Must be a flexible self-starter who can ramp up with new technologies, products, etc.
• Motivated, and able to work effectively under pressure
• Good written and oral communication skills
Education & Years of Experience
BS in Electrical Engineering or related + 6 years of experience, or MS + 3 years of experience, or Ph.D.
Location: Irvine, CA or San Diego, CA
Type: Full-time Employee
Digital Signal processing is key. Communication type design experience is a must have. Satellite, wireless etc understands communication theory and algorithms for ASIC RTL design. Fixed point implementation for blocks like Reedsolomon, FFT, LDPC, FIR IIR filters
Responsibilities
• Micro-architecture definition for communication/DSP functions including algorithm optimization feedback to Communication Systems team to minimize power and area
• RTL implementation in SystemVerilog/Verilog of communication/DSP functions
• Block-level verification including creation of Verilog or UVM testbenches
• System-level verification in UVM/SysC environment including test case creation/debug, functional coverage specification, and code coverage analysis
• Perform block-level preliminary synthesis and power estimation, including SDC constraint specification and vector-driven power analysis
• Perform block-level design checks including lint, CDC and DFT-readiness checks
• Support Emulator/FPGA-based verification including debug of SW driven test cases
• Post silicon bring-up support and silicon debug in lab
Qualifications
• Solid background in high-speed, low-power implementation of communication/DSP functions, including knowledge of communication/DSP theory and experience with fixed-point implementation
• Strong logical and creative problem-solving skills with excellent analytical and debugging skills
• Must be a flexible self-starter who can ramp up with new technologies, products, etc.
• Motivated, and able to work effectively under pressure
• Good written and oral communication skills
Education & Years of Experience
BS in Electrical Engineering or related + 6 years of experience, or MS + 3 years of experience, or Ph.D.